library ieee;
use ieee.std_logic_1164.all;

entity gatesTb is
end entity gatesTb;
--TODO ADD MORE TESTS!!!
architecture RTL of gatesTb is
	
signal X : bit := '1';
signal Y : bit := '1';
signal result : bit;
	
component and2
	
	port(a,b : in bit;
		z : out bit
	);
	
	
end component;

	for all : and2 use entity work.and2(DATAFLOW); 
	
begin

	and_1 : and2 port map (
		X, Y, result	
	);

	tb : PROCESS
		
	begin
	
	wait for 10 ns;
	X <= '0';
	wait for 10 ns;
	Y <= '0';
	wait for 10 ns;
	X <= '1';
	wait for 10 ns;
	Y <= '1';
	
	wait;
		
	end PROCESS;

end architecture RTL;
